Semiconductor device with MIS capacitors sharing dielectric film

ABSTRACT

A semiconductor device having an MIS capacitor having a low capacitance value and an MIS capacitor having a high capacitance value, and to a manufacturing method thereof. One MIS capacitor consists of a lower conductive material region formed on the substrate, a multilayer dielectric film consisting of a first insulating film, serving as both an interlayer insulating film and a dielectric film, and a second insulating film serving as a dielectric film of the other MIS capacitor, and an upper conductive material film, and the capacitance of the first MIS capacitor is determined by an area of the dielectric film formed by the second insulating film.

BACKGROUND OF THE INVENTION

The present invention relates to a semiconductor device and asemiconductor device manufacturing method, and more specifically relatesto a semiconductor device comprising a plurality of insulator capacitorsand a manufacturing method thereof.

BACKGROUND ART

A conventional example of an insulator capacitor (to be referred to as“MIS capacitor” hereinafter) will be described with reference to FIG. 4.FIG. 4 shows an MIS capacitor device formed in, for example, a bipolarIC. For example, in FIG. 4, an N type epitaxial layer 122 is formed on aP type semiconductor substrate 121, and a silicon oxide layer orso-called LOCOS 123 formed by local oxidation of silicon and a deviceisolation diffusion layer 124 consisting of a P type diffusion layer andformed below the LOCOS 123, both of which layers become a deviceisolation region, are formed on the epitaxial layer 122. The deviceisolation diffusion layer 124 is formed to reach the semiconductorsubstrate 121. An N type semiconductor region 113 doped with N typeimpurities is formed on the epitaxial layer 122 defined by the deviceisolation region. A conventional MIS capacitor 101 is constituted byforming an opening portion 127 in a first interlayer insulating film 126formed on a surface including a portion on the semiconductor region 113with the semiconductor region 113 serving as a lower electrode, formingan insulating film (or a so-called dielectric film) 111 on thesemiconductor region 113 facing this opening portion 127, and forming anupper electrode 112 of a polysilicon film on the insulating film 111.Further, a second interlayer insulating film 128 is formed to cover theupper electrode 112, a wiring 130 connected to the upper electrode 112through an opening portion formed at a position in the second interlayerinsulating film 128, which position corresponds to the upper electrode112, is formed, and a wiring 131 connected to the lower electrode 113through an opening portion formed at positions in the first and secondinterlayer insulating films 126 and 128, which positions correspond tothe lower electrode 113, is formed.

In case of this MIS capacitor 101, the effective area thereof isdetermined according to the area of the opening portion 127 in the firstinterlayer insulating film 126, and the capacitance value thereof isdetermined according to the property and thickness of the insulatingfilm (or dielectric film) 111 provided in the opening portion 127.Actually, however, even on the peripheral portion of the opening portion127, a parasitic capacitance is generated between the upper electrode112 and the lower electrode 113 with the first interlayer insulatingfilm 126 and the insulating film (or dielectric film) 111 put betweenthe upper and lower electrodes 112 and 113. This parasitic capacitanceis added to an overall capacitance value proportionally to theperipheral length of the upper electrode 112 and that of the insulatingfilm (or dielectric film) 111 on the peripheral portion of the openingportion 127.

Meanwhile, in case of the conventional semiconductor device, theapplicable capacitance value range of the MIS capacitor is often in theorder of 1 pF or more. It has hardly been assumed that capacitancevalues particularly in the applicable range of 100 fF or less are used.In particular, the required performance of the ordinary MIS capacitor isthat the MIS capacitor has a capacitance value used frequently, i.e., acapacitance value per unit area as high as possible in a region in theorder of pF to nF with a view of reducing the area of a circuit, a smallarea, high accuracy and high reliability. To meet this requirement, withan ordinary MIS capacitor formation technique, a silicon nitride (Si₃N₄)film [film thickness: about 20 nm to 50 nm] having a high dielectricconstant and advantageous in reliability is often used as the dielectricfilm. The capacitance value per unit area of the MIS capacitor havingthe structure stated above is about 1 fF/μm² to 3 fF/μm².

In recent years, as signal processing is accelerated, the frequency of,for example, the circuit for an optical pickup of an optical disk (CD,DVD or the like) or a so-called PDIC (photodiode integrated circuit)becomes higher and an MIS capacitor in a region having a capacitancevalue of 100 fF or less is required as an MIS capacitor in the circuit.

Using the circuit configuration of the PDIC shown in FIG. 5, an exampleof using the MIS capacitor in a region having a capacitance value of 100fF or less will be described. As shown in FIG. 5, an ordinary PDIC 140consists of a photodiode 141 serving as a current source and acurrent-voltage conversion circuit (or so-called IV amplifier) 142. Thephotodiode 141 equivalently consists of a junction capacitance C_(PD)and a photoelectric current i_(PD). The current-voltage conversioncircuit 142 has a differential amplifier A. A predetermined bias voltageVc is applied to a non-inverting input terminal of the differentialamplifier A and a cathode of the photodiode 141 is connected to ainverting input terminal of the differential amplifier A through awiring 143. A resistance R_(t) and a capacitance C_(t) are connected inparallel between the inverting input terminal of the differentialamplifier A and the output terminal t_(out) thereof from which an outputvoltage v_(o) is obtained. Reference symbol C_(H) denotes a wiringcapacitance.

The frequency of the current-voltage conversion circuit 142 is expressedby Mathematical Expression 1 using the resistance R_(t) and thecapacitance C_(t) shown in FIG. 5.

[Mathematical Expression 1]

f=1/(2π·R _(t) ·C _(t))

For example, if an output voltage v_(o) of 300 mV is necessary while thelight receiving sensitivity S of the photodiode is 0.4 A/W and laserpower P is 10 μW, the following relationship is obtained:

R _(t) =v _(o) /i _(PD)=300e ⁻³/(0.4×10e ⁻⁶)=75000 Ω=75k Ω

As the read/write rates of optical disks (e.g., CD and DVD) areaccelerated, demand for an improvement in the frequency characteristicsof the PDIC 140 arises. For example, the PDIC 140 is required to have acutoff frequency f_(c) of about 100 MHz of a 10 times speed DVD.

If it is assumed that the cutoff frequency f_(c) of the PDIC 140 israte-controlled by the frequency characteristics of the current-voltageconversion circuit 142, the required MIS capacitance C_(t) is obtainedusing the above [Mathematical Expression 1] as follows:

100MHz=1/(2π·75kΩ·C _(t))

C _(t)=2.1e ⁻¹⁴ [F]=21[fF]

However, if the conventional MIS capacitor 101 is used, the ratio of aparasitic capacitance on the peripheral portion of the MIS capacitor toa capacitance formed by the effective area (or the area of the so-calledopening portion 127) suddenly increases in a region having a capacitancevalue of 1 pF or less which is not supposed to fall in the applicablerange. In other words, if the capacitance value is about 1 pF or less,the influence of the parasitic capacitance on the peripheral portionincreases according to the increase of the peripheral length to arearatio of the MIS capacitor. Following this, the deterioration of theunevenness of the MIS capacitor resulting from the unevenness of theparasitic capacitance stated above (so-called controllability ofcapacitance value) becomes conspicuous. Taking an MIS capacitor in acurrently conducted manufacturing process as an example, the unevennessof the MIS capacitor with a capacitance value of 10 fF is approximately±50% (see a second MIS capacitor curve II shown in FIG. 2).

Under these circumstances, it is necessary to develop a semiconductordevice having an MIS capacitor having a high capacitance value (e.g., ina region having a capacitance value exceeding 100 fF) and an MIScapacitor having a low capacitance value (e.g., in a region having acapacitance value of 100 fF or less) mounted on a common semiconductorsubstrate. In the development of the semiconductor device of this type,it is demanded that the unevenness of capacitance values is suppressedto be little within a practicable range while suppressing the occupiedarea of each MIS capacitor within a predetermined allowable range on anintegrated circuit, and that the semiconductor device of this type canbe manufactured without increasing the number of manufacturing steps.

SUMMARY OF THE INVENTION

The present invention provides a semiconductor device and asemiconductor device manufacturing method made to solve the above-stateddisadvantages.

A semiconductor device according to the present invention is asemiconductor device comprising a first insulator capacitor formed on asubstrate; and a second insulator capacitor formed on the substrate, andhaving a higher capacitance than a capacitance of the first insulatorcapacitor, wherein the first insulator capacitor is constituted out of afirst conductive material region formed on the substrate; a firstinsulating film serving as both an interlayer insulating film and adielectric film of the first insulator capacitor, and formed on thefirst conductive material region; a second insulating film serving as apart of the dielectric film of the first insulator capacitor and adielectric film of the second insulator capacitor, and formed on thefirst insulating film; and a conductive material film formed on thesecond insulating film, and the capacitance of the first insulatorcapacitor is determined by a formation area of the dielectric film firstconductive material film.

The first insulating film can be formed out of a single or a pluralityof silicon oxide layers, and the second insulating film is formed out ofa silicon nitride layer.

A capacitance value of the first insulator capacitor can be set at notmore than 100 fF.

Also, a capacitance value of the first insulator capacitor can be set atnot more than 100 fF, and a capacitance value of the second insulatorcapacitor can be set at a value exceeding 100 fF.

In the above-stated semiconductor device, the dielectric film of thefirst insulator capacitor is constituted out of the first insulatingfilm and the second insulating film to thereby make the dielectric filmthick, and the second insulating film is formed out of, for example, asilicon nitride film and the first insulating film is formed out of, forexample, a silicon oxide film having a lower dielectric constant thanthat of the second insulating film, whereby a capacitance value per unitarea is lowered, an MIS capacitor area is increased and a peripherallength to area ratio in a low capacitance region is made low. Bydetermining the capacitance value of the first insulator capacitoraccording to the area of the upper electrode (i.e., the dielectricfilm), a parasitic capacitance generated in the peripheral portion isreduced per se. The first insulator capacitor is constituted as statedabove, whereby the first insulator capacitor becomes a highly accurateinsulator capacitor corresponding to a low capacitance region of about10 fF to 100 fF. Accordingly, the first insulator capacitor is capableof suppressing the unevenness of capacitance values within a practicalrange while suppressing its occupied area to be small within apredetermined allowable range on an integrated circuit, and capable ofcorresponding to the low capacitance region having a requiredcapacitance value of 100 fF or less. Besides, the first insulatorcapacitor is highly accurate and excellent in reliability. In addition,since the silicon nitride film used for the conventional MIS capacitoris used as a part of the dielectric film, it is expected that the firstinsulator capacitor has a film property equivalent to or higher thanthat of the conventional MIS capacitor which film property influencesthe reliability of the MIS capacitor.

According to the present invention, the semiconductor device statedabove is constituted so that the first conductive material regionserving as a lower electrode of the first insulator capacitor and thesecond conductive material region serving as a lower electrode of thesecond insulator capacitor are formed in a common conductive materialregion; a part of the dielectric film of the first insulator capacitorand an insulating film having an opening portion determining thecapacitance of the second insulator capacitor are formed by the firstinsulating film; a remaining part of the dielectric film of the firstinsulator capacitor and the dielectric film of the second insulatorcapacitor are formed by the second insulating film; and an upperelectrode of the first insulator capacitor and an upper electrode of thesecond insulator capacitor are formed by a common conductive materialfilm.

By thus constituting the semiconductor device, it is possible tomanufacture a semiconductor device having the first insulator capacitorhaving a low capacitance value of 100 fF or less and the secondinsulator capacitor having a high capacitance value exceeding 100 fFprovided on a common substrate, without increasing the number ofmanufacturing steps.

A semiconductor device manufacturing method according to the presentinvention is a method of manufacturing a semiconductor device having afirst insulator capacitor and a second insulator capacitor formed on asemiconductor substrate, the first insulator capacitor and the secondinsulator capacitor having different unit capacitance values, the methodcomprising the steps of: doping the semiconductor substrate withimpurities, and forming a first conductive material region and a secondconductive material region; forming a first insulating film on the firstconductive material region and the second conductive material region,the first insulating film serving as both an interlayer insulating filmand a dielectric film of the first insulator capacitor; forming anopening portion of the first insulating film on the second conductivematerial region; forming a second insulating film on the firstinsulating film and in the opening portion, the second insulating filmserving as both a part of the dielectric film of the first insulatorcapacitor and a dielectric film of the second insulator capacitor; andforming a conductive material film on the second insulating film, theconductive material film serving as an upper electrode of the firstinsulator capacitor and an upper electrode of the second insulatorcapacitor, and wherein a capacitance of the first insulator capacitor isdetermined by a formation area of the conductive material film.

The first insulating film can be formed out of a single or a pluralityof silicon oxide films, and the second insulating film can be formed outof a silicon nitride film.

According to the semiconductor device manufacturing method stated above,the dielectric film of the first insulator capacitor is formed out ofthe first insulating film and the second insulating film to thereby makethe dielectric film thick, and the second insulating film is formed outof, for example, a silicon nitride film and the first insulating film isformed out of, for example, a silicon oxide film having a lowerdielectric constant than that of the second insulating film, whereby acapacitance value per unit area is lowered, an MIS capacitor area isincreased and a peripheral length to area ratio in a low capacitanceregion is made low. Further, by determining the capacitance valueaccording to the area of the upper electrode (or the dielectric film), aparasitic capacitance generated in the peripheral portion is reduced perse. By employing the above-stated manufacturing method, a highlyaccurate insulator capacitor corresponding to a low capacitance regionof about 10 fF to 100 fF is manufactured. Accordingly, the firstinsulator capacitor corresponding to the low capacitance region having arequired capacitance value of 100 fF or less can be formed whileensuring high accuracy and excellent reliability.

Moreover, since the silicon nitride film used for the conventional MIScapacitor is used as a part of the dielectric film, it is expected thatthe first insulator capacitor has a film property equivalent to orhigher than that of the conventional MIS capacitor which film propertyinfluences the reliability of the MIS capacitor. Besides, it is possibleto form the MIS capacitor from a normal bipolar transistor processwithout increasing the number of manufacturing steps.

Since there is no need to add a new step to the step of forming thesecond insulator capacitor so as to form the first insulator capacitor,no load is given to the process.

For the above-stated reasons, two types of insulator capacitor havingdifferent structures can be separately used for capacitance regions forwhich the respective capacitors are responsible, i.e., can be used in aregion having a value exceeding 100 fF and a region having a value of100 fF or less, respectively. Thus, compared with a conventional case,it is possible to provide highly accurate insulator capacitors in a widerange.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic block diagram showing a mode for carrying out theinvention according to the semiconductor device of the presentinvention.

FIG. 2 is a chart showing the relationships between the unevenness ofthe capacitance values of the first and second MIS capacitors,respectively.

FIG. 3A is a cross-sectional view for manufacturing steps showing themode for carrying out the invention according to the semiconductormanufacturing method of the present invention.

FIG. 3B is a cross-sectional view for manufacturing steps showing themode for carrying out the invention according to the semiconductormanufacturing method of the present invention.

FIG. 3C is a cross-sectional view for manufacturing steps showing themode for carrying out the invention according to the semiconductormanufacturing method of the present invention.

FIG. 3D is a cross-sectional view for manufacturing steps showing themode for carrying out the invention according to the semiconductormanufacturing method of the present invention.

FIG. 3E is a cross-sectional view for manufacturing steps showing themode for carrying out the invention according to the semiconductormanufacturing method of the present invention.

FIG. 3F is a cross-sectional view for manufacturing steps showing themode for carrying out the invention according to the semiconductormanufacturing method of the present invention.

FIG. 4 is a schematic, sectional block diagram showing a conventionalMIS capacitor.

FIG. 5 is a schematic circuit diagram showing the circuit configurationof a PDIC.

DETAILED DESCRIPTION OF THE INVENTION

A mode for carrying out the invention according to the semiconductordevice of the present invention will be described with reference to aschematic, sectional block diagram shown in FIG. 1. By way of example,FIG. 1 shows an insulator capacitor, i.e., a so-called MIS capacitorformed in an existing bipolar IC.

As shown in FIG. 1, an N type epitaxial layer 12 is formed on a P typesemiconductor substrate 11. A LOCOS 13 and a device isolation diffusionlayer 14 formed out of a P type diffusion layer and provided below theLOCOS 13, both of which serve as a device isolation region, are formedon this epitaxial layer 12. This device isolation diffusion layer 14 isformed to reach the semiconductor substrate 11. Also, on the epitaxiallayer 12 defined by the above device isolation region, a firstconductive material region 15 and a second conductive material region 16doped with N type impurities are formed out of an N⁺ type diffusionlayer having a diffusion depth from a substrate 1 Xj of about 0.5 μm, adensity of 1×10¹⁸ impurities/cm³ to 1×10²⁰ impurities/cm³. This firstconductive material region 15 becomes a lower electrode of the first MIScapacitor and the second conductive material region 16 becomes a lowerelectrode of the second MIS capacitor. The substrate 1 is thusconstituted.

A first insulating film 21 serving as an interlayer insulating film anda part of the dielectric film of the first insulator capacitor (to bereferred to as “first MIS capacitor” hereinafter) is formed out of, forexample, a silicon oxide film having a thickness of about 150 nm on thesurface of the substrate 1 (or epitaxial layer 12). It is noted that thesilicon oxide film may be replaced by a plurality of layers of siliconoxide films obtained by forming a thermal oxide film to have a thicknessof, for example, about 50 nm by thermal oxidation at about 900° C. andthen forming a silicon oxide film to have a thickness of, for example,about 100 nm by the chemical vapor deposition method in view of thereliability of a film property and the stability of a silicon interface.

An opening portion 22 is formed in the first insulating film 21 in aregion in which the second insulator capacitor (to be referred to as“second MIS capacitor” hereinafter) is formed. A second insulating filmused as a part of dielectrics of the first MIS capacitor and thedielectric film of the second MIS capacitor is formed out of, forexample, a silicon nitride film 23 having a thickness of about 40 nm onthe first insulating film 21 and in the inner surface of the openingportion 22. This second insulating film 23 is patterned to have apredetermined magnitude to function as a dielectric film. In this way, adielectric film 24 of the first MIS capacitor is formed out of the firstinsulating film 21 and the second insulating film 23. Also, thedielectric film 25 of the second MIS capacitor is formed out of thesecond insulating film 23. As a result, the reliability of the filmproperty of the first MIS capacitor is at least equivalent to or higherthan the reliability of the film property of the second MIS capacitor.

Further, a conductive material film 26 which becomes an upper electrode27 is formed on the second insulating film 23 in the region in which theabove-stated first MIS capacitor is formed, by depositing, for example,polysilicon with a thickness of about 200 nm. Also, a conductivematerial film 26 which becomes an upper electrode 28 is formed on thesecond insulating film 23 in the region in which the above-stated secondMIS capacitor is formed, by depositing, for example, polysilicon by athickness of about 200 nm.

That is to say, the first MIS capacitor 2 is constituted out of thefirst conductive material region 15, the first insulating film 21 (orsilicon oxide film), the second insulating film 23 (silicon nitridefilm) and the upper electrode 27, while the second MIS capacitor 3 isconstituted out of the second conductive material region 16, the secondinsulating film 23 (or silicon nitride film) and the upper electrode 28.It is noted that polysilicon films which resistivity is reduced byinjecting impurities by means of the ion implantation technique or thelike are employed as those constituting the upper electrodes 27 and 28,respectively. The effective area of the first MIS capacitor 2 isdetermined according to the area of the upper electrode 27. In addition,the effective area of the second MIS capacitor 3 is determined accordingto the opening area of the opening portion 22. It is noted that thepolysilicon films can also serve as normally employed polysiliconresistances or the like.

Moreover, a silicon oxide film 31, serving as an interlayer insulatingfilm, is formed on the first insulating film 21 to have a thickness of,for example, about 300 nm, so as to cover the first and second MIScapacitors 2 and 3. Opening portions 32 and 33 are formed in the siliconoxide film 31 on the upper electrodes 27 and 28, respectively andopening portions 34 and 35 reaching the first and second conductivematerial regions 15 and 16 are formed, respectively.

Furthermore, wirings 42 and 43 connected to the upper electrodes 27 and28 through the opening portions 32 and 33 are formed, respectively, andwirings 44 and 45 connected to the first and second conductive materialregions 15 and 16 through the opening portions 24 and 35 are formed,respectively. During the formation, the wiring 42 is formed inwardlycompared with the upper electrode 27, whereby it is possible to minimizethe influence of a parasitic capacitance due to the wiring 42. Each ofthe wirings 44 and 45 for taking out the lower electrodes is set to havea minimum width in a design rule, whereby it is possible to minimize theinfluence of a parasitic capacitance.

As stated so far, a semiconductor device is constituted so that twotypes of MIS capacitors having different capacitance values per unitarea, i.e., the second MIS capacitor (or MIS capacitor using the siliconnitride film of 40 nm in thickness as the dielectrics) 3 having aconventional structure of a capacitance value per unit area of 1.6fF/μm² and the first MIS capacitor (or MIS capacitor using the siliconoxide film of 150 nm in thickness and the silicon nitride film of 40 nmin thickness as the dielectrics) 2 having a capacitance value per unitarea of 0.2 fF/μm² are mounted on the same substrate.

In case of the above-stated semiconductor device, the dielectric film 24of the first insulator capacitor 2 is constituted out of the firstinsulating film (or silicon oxide film) 21 and the second insulatingfilm (or silicon nitride film) 23 to thereby make the dielectric film 24thick. In addition, the second insulating film 23 is formed out of, forexample, the silicon nitride film and the first insulating film 21 isformed out of the silicon oxide film having a lower dielectric constantthan that of the second insulating film 23, whereby a capacitance valueper unit area is lowered, an MIS capacitor area is increased and aperipheral length to area ratio in a low capacitance region is made low.Also, the capacitance value of the first MIS capacitor 2 is determinedaccording to the area of an electrode on one side (i.e., the conductivematerial film 26 serving as the upper electrode 27), whereby a parasiticcapacitance generated on the peripheral portion is reduced per se. Byemploying such a structure, a highly accurate MIS capacitorcorresponding to a low capacitance region of about 10 fF to 100 fF isprovided.

Additionally, since the silicon nitride film used for the conventionalMIS capacitor is used as a part of the dielectric film 24, the filmproperty of the dielectric film 24, which influences the reliability ofthe first MIS capacitor 2, is expected to be equivalent to or higherthan that of the conventional MIS capacitor.

Next, the relationship between the capacitance values of the first andsecond MIS capacitors 2 and 3 and the unevenness thereof will bedescribed with reference to FIG. 2. In FIG. 2, the vertical axisindicates the unevenness of the capacitance and the horizontal axisindicates the capacitance value of each MIS capacitor. The curve Iindicates the first MIS capacitance, and the curve II indicates thesecond MIS capacitance.

As shown in FIG. 2, if it is assumed that process unevenness (such asthe unevenness of film thicknesses/unevenness of patterning) relative tothe first MIS capacitor is equivalent to process unevenness relative tothe second MIS capacitor, the unevenness of the first MIS capacitor 2 isobviously about 22% to 18% in a region of capacitance calculated valuesof 10 fF to 100 fF, indicating that the accuracy of the first MIScapacitor 2 is superior to the accuracy of the second MIS capacitor 3.

Here, the first MIS capacitor 2 is used in a region having a capacitancevalue equal to or lower than a predetermined capacitance value and thesecond MIS capacitor 3 is used in a region having a capacitance valueexceeding the predetermined capacitance value. This predeterminedcapacitance value is determined based on a capacitance value at whichthe expected unevenness of capacitances resulting from the unevenness ofthe manufacturing processes or the like of the first MIS capacitor 2 isidentical to that of the second MIS capacitor 3. In case of FIG. 2, sucha predetermined capacitance value is 100 fF. That is, the first MIScapacitor 2 is used in a region having a capacitance value of 100 fF orless and the second MIS capacitor 3 is used in a region having acapacitance value exceeding 100 fF.

Next, a mode for carrying out the invention according to thesemiconductor device manufacturing method of the present invention willbe described with reference to cross-sectional views of manufacturingsteps shown in FIG. 3. By way of example, FIG. 3 shows an MIS capacitorformed in an existing bipolar IC. It is noted that the same constituentelements as those described with reference to FIG. 1 are denoted by thesame reference symbols.

As shown in FIG. 3A, an N type epitaxial layer 12 is formed on a P typesemiconductor substrate 11. Then, a device isolation region isconstituted by forming, for example, a LOCOS 13 and forming, below theLOCOS 13, a device isolation diffusion layer 14 of a P type diffusionlayer. Also, the N type epitaxial layer 12 is doped with N typeimpurities, thereby forming the first conductive material region 15 andthe second conductive material region 16 of N⁺ type each having adiffusion depth from a substrate 1 Xj of about 0.5 μm and a density of1×10¹⁸ to 10²⁰ impurities/cm³. This first conductive material region 15becomes the lower electrode of the first MIS capacitor and the secondconductive material region 16 becomes the lower electrode of the secondMIS capacitor. The substrate 1 is thus constituted.

Next, the first insulating film 21 which becomes an interlayerinsulating film and a part of the dielectric film of the first insulatorcapacitor (to be referred to as “first MIS capacitor” hereinafter) isformed out of, for example, a silicon oxide film having a thickness ofabout 150 nm on the substrate 1 (epitaxial layer 12). It is noted thatthe silicon oxide film may be replaced by a plurality of layers having astructure in which a thermal oxide film formed by thermal oxidation atabout 900° C. is formed to have a thickness of, for example, about 50 nmand then a silicon oxide film is formed to have a thickness of, forexample, about 100 nm by the chemical vapor phase deposition method.

Next, as shown in FIG. 3B, using ordinary lithographic technique andetching technique, an opening portion 22 is formed in the firstinsulating film 21 in a region in which the second insulator capacitor(to be referred to as “second MIS capacitor” hereinafter) is formed.Then, the second insulating film 23 used as a part of the dielectricfilm of the first MIS capacitor and the dielectric film of the secondMIS capacitor is formed out of, for example, a silicon nitride filmhaving a thickness of about 40 nm on the first insulating film 21 and onthe inner surface of the opening portion 22.

Next, as shown in FIG. 3C, using the ordinary lithographic technique andetching technique, the second insulating film 23 is patterned. Then, thedielectric film 24 of the first MIS capacitor is formed out of the firstinsulating film (or silicon oxide film) 21 and the second insulatingfilm (or silicon nitride film) 23. Also, the dielectric film 25 of thesecond MIS capacitor becomes the second insulating film (or siliconnitride film) 23. As a result, the reliability of the film property ofthe first MIS capacitor becomes at least equivalent to or higher thanthe dielectric constant of the second MIS capacitor.

Next, as shown in FIG. 3D, a conductive material film 26 is formed bydepositing, for example, polysilicon by a thickness of about 200 nm bythe chemical vapor phase deposition method. Then, using the knownlithographic technique and etching technique, the conductive materialfilm 26 is patterned to thereby form upper electrodes 27 and 28 of therespective MIS capacitors.

Namely, the first MIS capacitor 2 is constituted out of the firstconductive material region 15, the first insulating film (or siliconoxide film) 21, the second insulating film (or silicon nitride film) 23and the upper electrode 27, while the second MIS capacitor 3 isconstituted out of the second conductive material region 16, the secondinsulating film (or silicon nitride film) 23 and the upper electrode 28.

It is noted that polysilicon films which resistivity is reduced byinjecting impurities by the ion implantation technique or the like areused as those constituting the respective upper electrodes 27 and 28. Inaddition, the effective area of the first MIS capacitor 2 is determinedaccording to the area of the upper electrode 27 and the effective areaof the second MIS capacitor 3 is determined according to the openingarea of the opening portion 22. It is noted that the above-statedpolysilicon films can also serve as normally employed polysiliconresistances or the like.

Next, as shown in FIG. 3E, a silicon oxide film 31 which becomes aninterlayer insulating film is formed on the first insulating film 21 tohave a thickness of, for example, about 300 nm so as to cover the firstand second MIS capacitors 2 and 3. Following this, using thelithographic technique and the etching technique, opening portions 32and 33 are formed in the silicon oxide film 31 on the upper electrodes27 and 28, respectively and opening portions 34 and 35 reaching thefirst and second conductive material regions 15 and 16 are formed,respectively.

Next, as shown in FIG. 3F, using a film formation technique such assputtering or chemical vapor phase deposition method, a wiring layer 41is formed out of, for example, an aluminum based metallic film. Ifnecessary, it is preferable that a barrier metal layer or an adhesionlayer is formed. Then, using the lithographic technique, reactive ionetching technique or the like, the wiring layer 41 is processed tothereby form wirings 42 and 43 connected to the upper electrodes 27 and28, respectively, and wirings 44 and 45 connected to the first andsecond conductive material regions 15 and 16, respectively. During theformation, by forming the wiring 42 inwardly compared with the upperelectrode 27, it is possible to minimize the influence of a parasiticcapacitance caused by the wiring 42. In addition, each of the wirings 44and 45 for taking out the upper electrodes is set to have a minimumwidth in a design rule, thereby minimizing the influence of a parasiticcapacitance. Thereafter, using a known wiring process, the wirings areprocessed.

As stated so far, as the first and second MIS capacitors 2 and 3, twotypes of MIS capacitors having different capacitance values per unitarea, i.e., the second MIS capacitor (or MIS capacitor using the siliconnitride film of 40 nm in thickness as the dielectric film) 3 having theconventional structure having a capacitance value per unit area of 1.6fF/μm² and the first MIS capacitor (or MIS capacitor using the siliconoxide film of 150 nm in thickness and the silicon nitride film of 40 nmin thickness as the dielectrics) 2 having a capacitance value per unitarea of 0.2 fF/μm² can be formed simultaneously.

According to the above-stated semiconductor device manufacturing method,since the dielectric film 24 of the first MIS capacitor 2 is formed outof the first insulating film 21 and the second insulating film 23, thedielectric film 24 can be made thick. Besides, the second insulatingfilm 23 is formed out of, for example, a silicon nitride film and thefirst insulating film 21 is formed out of a silicon oxide layer having alower dielectric constant than that of the second insulating film,whereby a capacitance value per unit area is lowered, an MIS capacitorarea is increased and a peripheral length to area ratio in a lowcapacitance region is made low. Additionally, since the capacitancevalue is determined according to the area of the upper electrode 27 (orconductive material film 26) of the first MIS capacitor 2, a parasiticcapacitance generated on the peripheral portion is reduced per se.

By employing the above-stated manufacturing method, a highly accurateMIS capacitor corresponding to a low capacitance region of about 10 fFto 100 fF is manufactured. In addition, since the silicon nitride filmused for the conventional MIS capacitor is used as a part of thedielectric film, the MIS capacitor is expected to have a film property,influencing the reliability of the MIS capacitor, equivalent to orhigher than that of the conventional MIS capacitor. Besides, the MIScapacitor can be formed by an ordinary bipolar transistor processwithout increasing the number of manufacturing steps.

According to the semiconductor device stated above, the dielectric filmof the first MIS capacitor is formed out of the first insulating filmand the second insulating film to thereby make the dielectric filmthick, to lower a capacitance value per unit area, to increase an MIScapacitor area and to make a peripheral length to area ratio in the lowcapacitance region low. In addition, since the capacitance value of thefirst MIS capacitor is determined according to the formation area of theconductive material film serving as the upper electrode, the MISinsulator capacitor can correspond to a low capacitance region having arequired capacitance value of about 100 fF or less. Besides, since aparasitic capacitance generated on the peripheral portion is reduced perse, the insulator capacitor is highly accurate and excellent inreliability. Moreover, since the silicon nitride film used for theconventional MIS capacitor is used as a part of the dielectric film, itis expected that the insulator capacitor has a film property, whichinfluences the reliability of the MIS capacitor, equivalent to or higherthan that of the conventional MIS capacitor.

According to the semiconductor device manufacturing method of thepresent invention, the first insulator capacitor corresponding to a lowcapacitance region having a required capacitance value of about 100 fFor less can be formed while ensuring high accuracy and excellentreliability. In addition, since there is no need to add a new step tothe step of forming the second insulator capacitor so as to form thefirst insulator capacitor, no process load is generated.

According to the present invention, it is possible to provide asemiconductor device having an MIS capacitor having a high capacitancevalue (e.g., in a region having a capacitance value exceeding 100 fF)and an MIS capacitor having a low capacitance value (e.g., in a regionhaving a capacitance value of 100 fF or less) mounted on a commonsemiconductor substrate. In this connection, it is possible tomanufacture a semiconductor device of this type while suppressing theoccupied area of each MIS capacitor to be small within a predeterminedallowable range of an integrated circuit and suppressing the unevennessof capacitance values within a practicable range, without increasing thenumber of manufacturing steps.

What is claimed is:
 1. A semiconductor device comprising: a firstinsulator capacitor formed on a substrate; and a second insulatorcapacitor formed on said substrate; and having a higher capacitance thana capacitance of said first insulator capacitor, characterized in thatsaid first insulator capacitor is comprised of a first diffusion regionserving as a lower electrode formed on said substrate, a firstinsulating film serving as both an interlayer insulating film and adielectric film of the first insulator capacitor, and formed on saidfirst diffusion region, a second insulating film serving as a part ofthe dielectric film of the first insulator capacitor and formed on saidfirst insulating film, and a conductive material film formed on saidsecond insulating film serving as an upper electrode; said secondinsulator capacitor is comprised of a second diffusion region serving asa lower electrode formed on said substrate, said second insulating filmserving as a dielectric layer and formed on said second diffusionregion, and a conductive material formed on said second insulating filmserving as an upper electrode; and the capacitance of said firstinsulator capacitor is determined by a formation area of said dielectricfilm.
 2. The semiconductor device according to claim 1, characterized inthat said first insulating film is formed out of a single or a pluralityof silicon oxide layers; and said second insulating film is formed outof a silicon nitride layer.
 3. The semiconductor device according toclaim 1, characterized in that a capacitance value of said firstinsulator capacitor is not more than 100 fF.
 4. The semiconductor deviceaccording to claim 1, characterized in that a capacitance value of saidfirst insulator capacitor is not more than 100 fF; and a capacitancevalue of said second insulator capacitor exceeds 100 fF.
 5. Thesemiconductor device according to claim 1, characterized in that saidfirst diffusion region serving as a lower electrode of said firstinsulator capacitor and the second diffusion region serving as a lowerelectrode of said second insulator capacitor are formed in a; the partof the dielectric film of said first insulator capacitor and aninsulating film having an opening portion determining the capacitance ofsaid second insulator capacitor are formed by said first insulatingfilm; a remaining part of the dielectric film of said first insulatorcapacitor and the dielectric film of said second insulator capacitor areformed by said second insulating film; and the upper electrode of saidfirst insulator capacitor and the upper electrode of said secondinsulator capacitor are formed by a common conductive material film.